Von Neumann architecture, CPU components, registers and the fetch-decode-execute cycle. Sourced directly from Seaford's Craig 'n' Dave slides.
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Craig 'n' Dave · Edexcel 1CP2CPU Components and their Function
Craig 'n' Dave · Edexcel 1CP2The Fetch-Execute Cycle
Key facts
Von Neumann architecture
Based on the stored program concept — both instructions and data are held in the same main memory (RAM)
CPU components: Control Unit (CU), Arithmetic Logic Unit (ALU), registers
CU — sends signals to control how data moves around the CPU; decodes instructions
ALU — performs arithmetic calculations and logical decisions
Clock — synchronises components by generating pulses at a constant rate (e.g. 3GHz = 3 billion cycles/second)
Registers — must know all four
Program Counter (PC) — holds the address of the next instruction to be executed
Memory Address Register (MAR) — holds the address that data needs to be read from or written to
Memory Data Register (MDR) — holds data or instructions that have just been fetched from or are about to be written to memory
Accumulator (ACC) — general-purpose register; holds the result of ALU operations
Fetch-Decode-Execute cycle — step by step
FETCH: PC is checked → address copied to MAR → instruction fetched from RAM into MDR → PC incremented to next address
DECODE: CU decodes the instruction in the MDR to determine what needs to be done
EXECUTE: Instruction is carried out — e.g. data fetched from RAM, arithmetic performed in ALU, result stored in Accumulator
This cycle happens billions of times per second on a modern CPU
Exam questions — 5 questions · 12 marks
⚡ This module includes extended questions (4–6 marks). Read the hint. Write in full linked sentences. The AI will tell you exactly which mark scheme points you missed.
1 markCPU componentsEdexcel 1CP2 style
What is the role of the Control Unit (CU) in the CPU?
A Performs arithmetic and logical calculations
B Holds the address of the next instruction to be executed
C Sends signals to control how data moves around the CPU and decodes instructions
D Temporarily stores the result of arithmetic operations
1 markRegistersEdexcel 1CP2 style
After an instruction is fetched from memory, what is incremented?
A The Memory Address Register
B The Program Counter
C The Accumulator
D The Memory Data Register
4 marksFetch-Execute cycleEdexcel 1CP2 style
Describe the three stages of the fetch-decode-execute cycle. For each stage, state what happens. (4 marks)
Hint: Cover all three stages in order. For fetch, mention PC, MAR and MDR. For decode, mention the CU. For execute, give an example.
+40 XP
1 markClock speedEdexcel 1CP2 style
A CPU has a clock speed of 2GHz. How many fetch-execute cycles does it complete per second?
A 2,000
B 2,000,000
C 2,000,000,000
D 20,000,000
4 marksCompare CPU performance factorsEdexcel 1CP2 style
Explain how clock speed and cache memory affect the performance of a CPU. (4 marks)
Hint: Cover clock speed (what it is + how it affects performance) then cache (what it is + why it speeds things up). Two marks available for each.